FEDEVEL
Platform forum

Fazy , 03-21-2024, 07:34 PM

I wrote a longer letter beforehand in this topic to @Robert Feranec and I was advised to reach the community out here.

TLDR: This project aim to have A PoE based device, where I can get 5/9/12/20V DC output, and also forward the ethernet connection which support 1Gbit at least. My goal is to power non PoE devices from PoE Switch which on UPS for my smart home stuff. (Philips Hue HUB for example)

The letter and the attachment picture will be attached to the post.

Regards:
Peter (aka Fazy)

Fazy , 03-21-2024, 07:35 PM

QDrives , 03-23-2024, 02:57 PM

Q: What is the optimal place in the stackup to route the ethernet pairs?
A: They should have a reference plane below and/or above them.

I would not route signals on the top layer below the ethernet connectors. They are metallic and can cause shorts and/or change the characteristic impedance.


Q: Should I correct the length between the pairs?
A: For a small/simple board like this I would do it.


Keep at least 4 layers for this design.
Your feedback signal of the DC/DC converter uses the most bad solution. Never route it near and especially below the inductor!
Keep the 'switch node' (U4->L1) as short/small as possible.
Place C14 and C15 closer to the regulator. R15 and R16 can probably be moved further away.

Fazy , 03-23-2024, 03:06 PM

Thanks for the feedback @QDrives ! I'll look into it soon 🙂

Fazy , 03-23-2024, 03:10 PM

In ethernet terms: what should I think as reference? I think, because those are pairs, every pair is just reference to the significant other, since in ethernet, there are no common line, where the current flows back.

Fazy , 03-23-2024, 03:13 PM

https://resources.altium.com/p/gigabit-ethernet-101-basics-implementation
Based on this guide, I shoud create a separate copper layer, not connected to anything?

Fazy , 03-23-2024, 08:18 PM

Or... may I connect the reference plane to the shield?... (for both of the connectors?) Sorry for dumb questions, but I'm so confused in this topic...

Fazy , 03-24-2024, 12:50 PM

In the meantime, I played with a new design (replaced the out port to TH) where I route 3 pairs in Inner1, and the last one on Bottom layer. The paths has equal lenght for each pair now, and I not used any vias along the way

Fazy , 03-24-2024, 12:50 PM

Fazy , 03-24-2024, 12:54 PM

The chassis of the two ethernet connectors will be connected by a copper layer in Inner2, and Top, and the DC component will be routed out on the Bottom layer.. at least, this is my plan (still confused, where the hell I should join (or not...) the connectors metal chassis, since this project not have any ground connection, and will be in a plastic case)

QDrives , 03-24-2024, 07:12 PM

Signals on a board reference more the plane below it than the trace next to it.
Do note that the picture you show from Altium resources are the signals between the magnetics and connector. You have the magnetics inside of the connector.

What I would do is call the Gnd net "minus", VCC to "plus" and PSUGnd to Gnd.
Have a single Gnd plane and perhaps a small section also minus as a plane below the input of the TPS2375DR. Place a capacitor then over both planes to connect then (for high frequency). Parallel to a high value resistor.
The shield of the connectors also connected to Gnd.

Fazy , 03-24-2024, 08:08 PM

Hmm.. sounds legit... I know that multiple GND planes hardly a good way, so I'll reroute/rename what need to be renamed 🙂 About the placement of the buck converter, I played with this aswell

Fazy , 03-24-2024, 08:09 PM

Just don't mind the other stuff on the left... The capacitors moved more closer to the IC, and the feedback line is far away from the inductor, and everything else...

Fazy , 03-24-2024, 08:12 PM

And under the circuit, there are 3 layers of PSUGND.. Are there any downside using a lot of via to link the ground planes under each other? Can it be too much? 😄

QDrives , 03-25-2024, 07:30 PM

Q: Are there any downside using a lot of via to link the ground planes under each other?
A: You will have a nightmare soldering D1, U4, C13, R17, C6 and C7 as there is no thermal relief. With all the vias, you need to heat up multiple layers.

Q: Can it be too much?
A: Yes. 1) It can cost a bit more (holes/dm²), 2) Thermal relief as mentioned before. 3) Hole to hole clearance.
For the rest, no, not too much.

Fazy , 03-25-2024, 08:05 PM

My plan is to order with the SMT process... not as cheap as I want, but the quality looks ok, and spare me a lot of time (also.. I not have the equipment to solder SMD stuff yet :/ )

Fazy , 03-25-2024, 08:08 PM

Thanks again for helping me, the design was definitely improved in a last few days! 🙂 I'll wrote about it, once I got the package, and designed/printed the case, and have the first one running

QDrives , 03-26-2024, 04:30 PM

"I not have the equipment to solder SMD stuff yet" -- You do not have BGA/LGA on your board, so everything can be hand soldered.